Semiconductor Failure Analysis: Deprocessing Modern Devices

What Is Deprocessing?

Deprocessing is the controlled removal of semiconductor device layers to reveal underlying structures and failure sites. Modern ICs are three-dimensional structures: a silicon substrate containing transistors, covered by multiple layers of metal interconnects separated by interlayer dielectrics, topped by a final passivation layer. A defect responsible for a device failure may be located at any layer in this stack — and reaching it requires removing all layers above it without disturbing the defect or the surrounding structures.

The fundamental objective is to expose the failure site while preserving sufficient structural context for meaningful inspection and analysis.

Deprocessing Approaches by Device Type

Non-Planar (Older Process) Devices

Relatively simple ICs and those fabricated on older processes are typically constructed using non-planar technologies — bipolar, CMOS with relatively large feature sizes, and older analog devices. Deprocessing of these devices is typically accomplished using wet chemical etching, alternating between etching away metals and oxides with selective chemical solutions until the defect site is exposed.

Careful control of etch chemistry is essential: excess chemical reactivity can remove too much material, causing the circuit structures to dissolve entirely and leaving only a bare silicon substrate — potentially destroying all analytical value. The target is selective, controlled removal that exposes one layer at a time.

Planar (Modern Process) Devices

Modern high-speed processors, memory devices, and advanced logic ICs are fabricated using planar technologies that integrate many layers of metal interconnects—sometimes more than 15—with dielectric spacings measured in hundreds of angstroms. The traditional approach to deprocessing these devices is parallel lapping: using an extremely fine abrasive to remove material layer by layer progressively.

The margin for error in lapping modern devices is extraordinarily thin. With interlayer spacings of approximately 1,000 angstroms (for comparison, a human hair averages approximately one million angstroms thick), an analyst working at the boundary between two metal layers operates with essentially zero margin before causing irreparable damage.

An alternative approach — used when backside access is feasible — is to dissolve the silicon substrate chemically and inspect the circuitry from the back. This can reveal defects at diffusion and polysilicon layers, but is generally ineffective for defects buried between metal interconnect layers.

FIB as the Precision Alternative to Conventional Deprocessing

The Focused Ion Beam (FIB) has transformed deprocessing by providing a precision alternative to brute-force lapping or wet etching. Rather than removing entire layers across the chip surface, FIB allows an analyst to drill directly to the localized failure site — milling a precise cross-section through the exact feature of interest with nanometer-scale positional accuracy.

FIB deprocessing eliminates the surface-wide material removal of conventional techniques, preserving the structural context surrounding the failure site. Cross-sections prepared by FIB are then imaged by SEM and analyzed by EDS, providing both structural and compositional information about the defect at the atomic scale.

FIB also enables “micro-surgery” on failing devices: selectively cutting or rewiring metal traces to test the effect of specific changes on device function — a powerful technique during first-silicon evaluation when redesigning a mask set is cost-prohibitive.

Critical Considerations in Deprocessing

Correct process identification: The deprocessing technique must be matched to the device’s specific fabrication process. Applying non-planar deprocessing chemistry to a planar CMOS device — or vice versa — will result in catastrophic failure.

Layer-by-layer documentation: At each stage of deprocessing, the exposed surface is imaged and documented before the next layer is removed. This creates a complete record of the device’s structural integrity at each depth — essential for correlating electrical failure data with physical findings.

Failure isolation before deprocessing: The failure site should be localized as precisely as possible — using emission microscopy, OBIRCH, or thermal imaging — before deprocessing begins. Deprocessing a large device area without guidance on failure sites wastes time and risks destroying key evidence.

Conclusion

Deprocessing is a critical step in semiconductor failure analysis, enabling controlled layer-by-layer removal to expose hidden defects within complex IC structures while preserving analytical integrity. By combining traditional methods with advanced techniques like FIB for precise, localized material removal, engineers can accurately identify failure sites, correlate physical defects with electrical performance, and drive effective design and process improvements in modern semiconductor devices.

Infinita Lab’s Semiconductor Deprocessing Services

Infinita Lab provides semiconductor deprocessing and failure analysis services through its nationwide network of specialized semiconductor laboratories. Services include wet chemical deprocessing, parallel lapping, backside substrate removal, FIB precision sectioning, SEM/EDS analysis at each deprocessing stage, and the preparation of a complete failure analysis report. Expert IC failure analysis engineers apply the correct technique for each device type and process generation.

Contact Infinita Lab: (888) 878-3090 | www.infinitalab.com

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