Using FIB for Wafer Lot Acceptance & Design Verification: Applications Guide

Written by Dr. Bhargav Raval | Updated: April 4, 2026

What Is FIB and Why Is It Used in Semiconductor Analysis?

Focused Ion Beam (FIB) technology uses a finely focused beam of gallium ions to mill, image, deposit, and prepare nanoscale samples on semiconductor wafers and electronic components. In the semiconductor industry, FIB is an indispensable tool for two critical applications: wafer lot acceptance testing (verifying production conformance) and design verification (confirming that fabricated devices match design intent at the nanometre scale).

As semiconductor process nodes shrink below 5 nm and device structures become three-dimensional (FinFET, GAA nanosheet), the ability to cross-section, image, and analyse specific device features with nanometre precision becomes essential for maintaining yield and quality.

FIB for Wafer Lot Acceptance Testing

What Is Wafer Lot Acceptance?

Wafer lot acceptance is the process of verifying that a production wafer lot conforms to the process specification before it is released for further fabrication, assembly, or shipping. Critical dimensions (CD), film thicknesses, contact hole sizes, and layer-to-layer alignment must all fall within the process window defined for the product.

FIB Cross-Section for Physical Verification

FIB milling creates precise cross-sections through specific features — individual transistors, contact vias, metal interconnect lines, and gate stacks — at the exact locations defined by design coordinates, achieving ±50 nm accuracy on a patterned wafer. The cross-sectioned surface is immediately imaged by SEM (in the same FIB/SEM dual-beam instrument) to measure:

Gate oxide thickness: Verifying EOT (Equivalent Oxide Thickness) target within ±0.5 nm tolerance
Gate electrode CD: Critical dimension of the poly or metal gate at the channel
Contact hole dimensions: Opening size and taper angle for contacts and vias
Film stack layer thicknesses: Each deposited layer in the gate stack, interconnect, or passivation layer
Barrier and liner conformality: Coverage of thin barrier metals in high-aspect-ratio features

These physical measurements validate the electrical test data and provide direct evidence of process conformance that wafer-level electrical test (WLT) alone cannot supply.

EDS Analysis for Material Verification

FIB/SEM equipped with EDS simultaneously provides elemental composition verification for each film in the device stack — confirming correct material deposition (e.g., HfO₂ vs. SiO₂ for a high-k gate dielectric, cobalt vs. tungsten for a contact fill).

FIB for Design Verification

What Is Design Verification in Semiconductors?

Design verification confirms that the physical device structure, as fabricated, matches the design intent in the technology design kit (TDK) and the e-layout. At advanced nodes, even sub-nm deviations from design intent in gate dimensions or layer thicknesses can shift electrical characteristics outside the modelled performance range.

FIB/TEM for Atomic-Scale Verification

For the most critical device characterisation — particularly gate stack metrology — FIB prepares electron-transparent TEM lamellae (50–100 nm thick) from specific device features. STEM-EDS and EELS (electron energy loss spectroscopy) in the TEM provide atomic-resolution elemental maps of gate dielectric stoichiometry, interface layer composition, and dopant distribution:

High-k dielectric composition: Confirming hafnium content in HfO₂ or HfSiO high-k dielectrics
Interface trap layer quality: Characterising the Si/SiO₂ interface structure that governs gate leakage and reliability
Metal gate work function layer: Verifying titanium nitride thickness and composition that sets the threshold voltage

Circuit Edit for Debug Acceleration

FIB enables circuit modifications at the transistor level — cutting connections, depositing new metal bridges — to implement design changes on a physical device without fabricating a new mask set. This accelerates debug cycles from weeks (mask re-spin) to days, enabling faster design verification.

Industrial Applications

Leading semiconductor manufacturers (Intel, TSMC, Samsung) use FIB/SEM as a routine production monitoring tool, performing FIB cross-sections on monitor wafers at defined process steps to verify layer stack integrity. Contract IC design houses use FIB/TEM for physical design verification before product sign-off. Memory manufacturers use FIB cross-sections to verify bit-cell geometry and layer-thickness uniformity across wafer lots

Conclusion

Focused Ion Beam (FIB) technology is a critical tool in semiconductor analysis, enabling precise nanoscale cross-sectioning, imaging, and sample preparation required for modern device characterisation. By supporting wafer lot acceptance through accurate physical verification and enabling design validation at nanometre and atomic scales, FIB ensures that fabricated devices meet strict process and performance requirements. Its ability to combine structural analysis, material verification, and even circuit modification makes it indispensable for maintaining yield, accelerating development cycles, and ensuring reliability in advanced semiconductor manufacturing.

Why Choose Infinita Lab for FIB Analysis Services?

Infinita Lab provides FIB cross-sectioning, SEM/EDS analysis, and FIB-TEM lamella preparation for wafer lot acceptance and design verification through our nationwide accredited semiconductor analytical laboratory network.

Looking for a trusted partner to achieve your research goals? Schedule a meeting with us, send us a request, or call us at (888) 878-3090 to learn more about our services and how we can support you.

Frequently Asked Questions (FAQs)

What accuracy can FIB achieve in targeting a specific device feature on a patterned wafer?

Modern dual-beam FIB/SEM systems achieve site-specific navigation accuracy of ±50–100 nm using electron beam imaging and design data overlay (CAD navigation), enabling cross-sections through individual transistors or specific via sites in a 5 nm node product.

How thick is a TEM lamella prepared by FIB and why does it need to be so thin?

FIB-prepared TEM lamellae are typically 50–100 nm thick — thin enough for the 100–300 kV electron beam to transmit through the sample in the TEM, enabling atomic-resolution imaging. The thinning is performed in several stages: coarse milling removes bulk material; fine milling at low kV (2–5 kV) minimises gallium implantation damage in the final lamella surface.

Can FIB damage the device structure it is cross-sectioning?

FIB milling does introduce gallium ion implantation and lattice damage into the milled surfaces — but only to depths of ~20–30 nm for standard 30 kV gallium FIB. Final low-kV cleaning steps minimise this damage layer. Protective metal deposition (platinum or tungsten) on the feature of interest before FIB milling prevents the milling from damaging the device structure being cross-sectioned.

What is circuit edit using FIB and when is it used in design verification?

Circuit edit uses FIB milling to cut metal interconnects and FIB-induced CVD deposition to add new metal connections, implementing design changes on a physical test chip. It is used during design debug to verify whether a proposed design fix corrects an electrical failure without waiting for a new mask set fabrication — typically saving 4–8 weeks of debug cycle time.

How does FIB wafer lot acceptance complement electrical test data?

Electrical WLT measures device performance parameters (Vt, Ioff, Ion) but cannot directly measure physical dimensions or film thicknesses — they are inferred indirectly. FIB cross-sections provide the physical dimensional and compositional evidence that either confirms the process is in control (explaining good electrical data) or identifies the physical root cause of electrical excursions (unexpected thickness, CD drift, wrong material). Both are needed for complete process control.